Magnetic memory circuits are based on the magneto-resistive behavior of magnetic storage elements that are integrated typically with a complementary metal-oxide-semiconductor (CMOS) technology. Such memory circuits generally provide non-volatility and an unlimited read and write capability. An example is the magnetic random access memory (MRAM) circuit that includes a plurality of memory cells, each defining an addressable magnetic storage element that may include a magnetic tunnel junction (MTJ) stack.
Each addressable MTJ stack can have a magnetic spin orientation and can be flipped between two states by the application of a magnetic field that is induced by energizing corresponding bit and word lines.
FIG. 1A illustrates a plan view of a section of an exemplary array 100 of memory cells X 112 in a magnetic random access memory (MRAM) circuit, that includes a set of longitudinal word lines (WL) 102 and a set of transverse bit lines (BL) 104. The set of BL 104 overlies the set of WL 102 to define crossover zones 108. An addressable MTJ stack 110 is disposed within each crossover zone 108. Current drivers 106 are provided for energizing the BL 104 and the WL 102. An address transistor (not shown) is provided under each MTJ stack 110 and in the memory cell X 112, for reading the state of the MTJ stack 110.
FIG. 1B illustrates a partly schematic and partly cross-sectional view of the memory cell X 112 in FIG. 1A. As shown in the cross-sectional view, the MTJ stack 110 is disposed within the crossover zone 108. The address transistor 132 is shown schematically. Generally, the MTJ stack 110 is designed to be integrated into a back-end metallization structure following a front-end CMOS processing. The MTJ stack 110 is shown to be provided between a first metallization layer Mx and a second metallization layer My, wherein the MTJ stack 110 is connected to the first layer Mx through a via hole 128 and to the second layer My through a via hole 116. The second layer My is patterned to include the BL 104. The MTJ stack 110 includes a free layer 118, a tunnel oxide layer 120, a fixed layer 122 and an extended bottom electrode 124. The first layer Mx is patterned to include the WL 102 for writing into the MTJ stack 110. The address transistor 132 is connected to the first layer Mx by a connection 130a. A read word line (WL) 130b in the first layer Mx is usable for selectively operating the address transistor 132. The WL 102 has no contact with the bottom electrode 124, and when energized, induces a magnetic field within the MTJ stack 110.
A write operation in a selected memory cell X 112 in the array 100 can be performed by energizing the corresponding BL 104 and the WL 102, to generate a changing the magnetic state of the corresponding MTJ stack 110. For a read operation, a voltage is applied to the BL 104 of the selected memory cell X 112, so that a current can flow through the corresponding MTJ stack 110 and the address transistor 132 that is selectively switched on by the WL 130b. The magnitude of the current sensed indicates the conductivity or the magnetic state of the MTJ stack 110.